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High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver(R) AD8382
PRODUCT FEATURES
High accuracy, high resolution voltage outputs 12-bit input resolution Laser trimmed outputs Fast settling, high voltage drive 33 ns settling time to 0.25% into 200 pF load Slew rate 390 V/s Outputs to within 1.3 V of supply High update rates Fast, 120 Ms/s data update rate Voltage controlled video reference (brightness) and full-scale (contrast) output levels Flexible logic STSQ/XFR allow parallel AD8382 operation INV bit reverses polarity of video signal Output overload protection Low static power dissipation: 743 mW Includes STBY function 3.3 V logic, 9 V to 18 V analog supplies Available in 48-lead 7 mm x 7 mm LFCSP
FUNCTIONAL BLOCK DIAGRAM
DB(0:11)
12
12
12 2-STAGE 12 LATCH 12 2-STAGE 12 LATCH 12 2-STAGE 12 LATCH 12 2-STAGE 12 LATCH 12 2-STAGE 12 LATCH 12 2-STAGE 12 LATCH
DAC
VID0
AD8382
DAC
VID1
DAC
STBY BYP
VID2
BIAS
DAC
VID3
DAC
R/L E/O CLK STSQ XFR SEQUENCE CONTROL
VID4
DAC
VID5
SCALING CONTROL VREFHI VREFLO INV V1 V2
APPLICATIONS
LCD analog column driver
Figure 1. Functional Block Diagram
PRODUCT DESCRIPTION
The AD8382 DecDriver provides a fast, 12-bit latched decimating digital input that drives six high voltage outputs.12-bit input words are sequentially loaded into six separate, high speed, bipolar DACs. A flexible digital input format allows several AD8382s to be used in parallel for higher resolution displays. STSQ synchronizes sequential input loading, XFR controls synchronous output updating, and R/L controls the direction of loading as either left-to-right or right-to-left. Six channels of high voltage output drivers drive to within 1.3 V of the rail. The output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility. The AD8382 is fabricated on Analog Devices' XFHV, fast bipolar 26 V process, providing fast input logic bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. The AD8382 dissipates 743 mW nominal static power. The STBY pin reduces power to a minimum, with fast recovery.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD8382
TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Timing Characteristics..................................................................... 6 Pin Configuration and Functional Descriptions.......................... 7 Typical Performance Characteristics ............................................. 8 Functional Description .................................................................. 13 Transfer Function ....................................................................... 13 Accuracy ...................................................................................... 14 Applications..................................................................................... 15 VBIAS Generation--V1, V2 Input Pin Functionality ........... 17 Power Supply Sequencing ......................................................... 18 PCB Design for Optimized Thermal Performance ............... 18 Layout Considerations............................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8382
SPECIFICATIONS
Table 1. @ 25C, AVCC = 15.5 V, DVCC = 3.3 V, TMIN = 0C, TMAX = 85C, VREFHI = 9.5 V, VREFLO = V1 = V2 = 7 V, unless otherwise noted.
Parameter VIDEO DC PERFORMANCE VDE VCME
1
Conditions TMIN to TMAX DAC Code 1500 to 3200 DAC Code 1500 to 3200 DAC Code 2048 DAC Code 0 to 4095 TC, MIN to TC, MAX, VO = 5 V Step, CL = 200 pF 20% to 80% 20% to 80%
Min -5 -3.5
Typ
Max +5 +3.5 7.5 15
Unit mV mV mV mV
V V VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% Invert Switch Overshoot CLK and Data Feedthrough2 All-Hostile Crosstalk3 Amplitude Duration DAC Transition Glitch Energy VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing CLK to VID Delay: t94 INV to VID Delay: t10 Output Current Output Resistance RESOLUTION Coding DIGITAL INPUT CHARACTERISTICS Max. Input Data Update Rate Data Setup Time: t1 STSQ Setup Time: t3 XFR Setup Time: t5 Data Hold Time: t2 STSQ Hold Time: t4 XFR Hold Time: t6 CLK High Time: t7 CLK Low Time: t8 CIN IIH IIL--All Inputs except CLK IIL--CLK VIH VIL VTH
+0.5 2.5 4
390 530 22 33 34 130 100 10 40 30 0.3 1.1 12 12.4 100 22
27 50 100 300 200
V/s V/s ns ns ns ns mV mV p-p mV p-p ns nV-s
Code 2047 to Code 2048 AVCC - VOH, VOL- AGND 50% of VIDx 50% of VIDx
10 10.4
1.3 14 14.4
V ns ns mA Bits Ms/s ns ns ns ns ns ns ns ns pF A A A V V V
Binary Input tr, tf = 2 ns (10% to 90%)
12 120 0 1 1 3 3 3 3 2.5 3 0.05 0.6 1.2 2 0.8 1.6
Rev. 0 | Page 3 of 24
AD8382
Parameter REFERENCE INPUTS1 V1 Range V2 Range V1 Input Current V2 Input Current VREFLO Range VREFHI Range (VREFHI - VREFLO) Range VREFHI Input Resistance VREFLO Bias Current VREFHI Input Current VFS Range POWER SUPPLY DVCC, Operating Range DVCC, Quiescent Current AVCC, Operating Range Total AVCC Quiescent Current STBY AVCC Current STBY DVCC Current OPERATING TEMPERATURE RANGE Ambient Temperature Range, TA Ambient Temperature Range, TA5 Junction Temperature Range, TJ Conditions V2 (V1 - 0.25 V) V2 (V1 - 0.25 V) Min 5 5 0.2 -7.5 VREFHI (VREFLO + 2.75 V) VREFHI (VREFLO + 2.75 V) V1 - 0.5 VREFLO 0 20 -0.2 125 VFS = 2 x (VREFHI - VREFLO) 3 9 STBY = HIGH STBY = HIGH Still Air 100% Tested 0 0 25 43 0.15 3.5 3.3 23 5.5 3.6 31 18 52 0.45 5 75 85 125 AVCC - 1.3 AVCC 2.75 Typ Max AVCC - 4 AVCC - 4 Unit V V A A V V V k A A V V mA V mA mA mA C C C
VDE = differential error voltage. VCME = common-mode error voltage. V = maximum deviation between outputs. Full-scale output voltage = VFS = 2 x (VREFHI - VREFLO). See the Accuracy section on page 14. 2 Measured on two outputs differentially as CLK and DB(0:11) are driven and STSQ and XFR are held LOW. 3 Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV. 4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV. 5 Operation at 85C ambient temperature requires a thermally optimized PCB layout (see Applications section), minimum airflow of 200 lfm, input clock rate not exceeding 120 MHz, black-to-white transition 4 V, and CL 200 pF.
1
Rev. 0 | Page 4 of 24
AD8382
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings1
Parameter Supply Voltages AVCCx to AGNDx DVCC to DGND Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltage Internal Power Dissipation2 LFCSP Package @ 25C Ambient Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec)
1
Rating 18 V 4.5 V DVCC + 0.5 V DGND - 0.5 V AVCC + 0.5 V AGND - 0.5 V 3.84 W 0C to 85C -65C to +125C 300C
MAXIMUM POWER DISSIPATION
The maximum power that the AD8382 can safely dissipate is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices, as determined by the plastic's glass transition temperature, is approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175C for extended periods can result in device failure.
OPERATING TEMPERATURE RANGE
Although the maximum safe operating junction temperature is higher, the AD8382 is 100% tested at a junction temperature of 125C. Consequently, the maximum guaranteed operating junction temperature is 125C. To ensure operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation to:
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum ratings for extended periods may reduce device reliability. 2 48-lead LFCSP Package: JA = 26C/W (JEDEC STD, 4-layer PCB in still air) JC = 20C/W. JB = 11C/W in Still Air
PDMAX where TJMAX = 125C
(TJMAX-TA ) ( JA -0.9 x 3 Airflow in lfm)
OVERLOAD PROTECTION
The AD8382 employs a two-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any output of the AD8382 is internally limited to 100 mA average. In the event of a momentary short circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection. The thermal shutdown "debiases" the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short circuit between a video output and power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typ. with a period set by the thermal time constant and hysteresis of the thermal trip point. The thermal shutdown provides long-term protection by limiting average junction temperature to a safe level.
AD8382 ON A 4-LAYER JEDEC PCB WITH THERMALLY OPTIMIZED LANDING PATTERN AS DESCRIBED IN THE APPLICATION NOTES 2.00 200 lfm 1.75 120MHz 500 lfm 1.50 STILL AIR 1.25 60Hz XGA
POWER DISSIPATION (W)
1.00 Quiescent
0.75
0.50
65
70
75
80
85
90
95
100
105
110
115
MAXIMUM AMBIENT TEMPERATURE (C)
Figure 2. Maximum Power Dissipation vs. Temperature.
Note: Quiescent power dissipation is 0.74 W when operating under the conditions specified in this data sheet.
EXPOSED PADDLE
To ensure a high degree of reliability, the exposed paddle must be electrically connected to AVCC. To ensure optimized thermal performance, the exposed paddle must be thermally connected to the AVCC plane as described in the Applications section.
When driving a 6-channel XGA panel with an input capacitance of 200 pF, the AD8382 dissipates a total of 1.14 W when displaying 1 pixel wide alternating white and black vertical lines generated by a standard 60 Hz XGA input video. The total power dissipation of the AD8382 is 1.67 W when operating at the maximum specified frequency of 120 MHz, under the conditions specified in this data sheet (Figure 2).
Rev. 0 | Page 5 of 24
AD8382
TIMING CHARACTERISTICS
Table 3. Timing Parameters and Conditions
Parameter t1, Data Setup Time t2, Data Hold Time t3, STSQ Setup Time t4, STSQ Hold Time t5, XFR Setup Time t6, XFR Hold Time t7, CLK High Time t8, CLK Low Time t9, CLK to VIDx Delay t10, INV to VIDx Delay To 50% of VIDx To 50% of VIDx Conditions tr, tf = 2 ns (10% to 90%) Min 0 3 1 3 1 3 3 2.5 10 10.4 12 12.4 14 14.4 Typ Max Unit ns ns ns ns ns ns ns ns ns ns
tf
CLK
tr t8 t7 t1 t2
VTH VTH
CLK
VTH
XFR
VTH
DB(0:11)
INV
STSQ VTH
VTH
t3
t4
VID(0:5)
VTH
50%
XFR
t5
t6
t9 t10
Figure 3. Timing Requirement E/O = HIGH
t8
CLK
Figure 5. Output Timing
t7
VTH
t1
DB(0:11)
t2
VTH
STSQ
t3
XFR VTH
t4
VTH
t5
t6
Figure 4. Timing Requirement E/O = LOW
Rev. 0 | Page 6 of 24
AD8382
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
41 AGNDDAC 42 AVCCDAC 39 VREFLO 40 VREFHI 37 AGND0 46 STSQ 48 CLK 47 XFR 45 NC 44 NC 43 V1 38 V2
DB0 1 DB1 2 DB2 3 DB3 4 DB4 5 DB5 6 DB6 7 DB7 8 DB8 9 DB9 10 DB10 11 DB11 12
PIN 1 INDICATOR
36 35 34 33
VID0 AVCC0,1 VID1 AGND1,2 VID2 AVCC2,3 VID3 AGND3,4 VID4 AVCC4,5 VID5 AGND5
AD8382
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
E/O 13
R/L 14
INV 15
DGND 16
DVCC 17
AVCCBIAS 18
NC 19
STBY 20
BYP 21
AGNDBIAS 22
NC 23
NC = NO CONNECT
Figure 6. 48-Lead LFCSP, 7 mm x 7 mm Package
Table 4. Pin Function Descriptions
Mnemonic DB(0:11) CLK STSQ Function Data Input Clock Start Sequence Description 12-Bit Data Input. MSB = DB(11). Clock Input. A new data loading sequence begins on the rising edge of CLK when this input was HIGH on the preceding rising edge of CLK and the E/O input is held HIGH. A new data loading sequence begins on the falling edge of CLK when this input was HIGH on the preceding falling edge of CLK and the E/O input is held LOW. A new data loading sequence begins on the left, with Channel 0, when this input is LOW, and on the right, with Channel 5, when this input is HIGH. The active CLK edge is the rising edge when this input is held HIGH and the falling edge when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is HIGH and on the falling edges when this input is LOW. Data is transferred to the outputs on the immediately following falling edge of CLK when this input is HIGH on the rising edge of CLK. These pins are directly connected to the analog inputs of the LCD panel. The voltages applied between these pins and AGND set the reference levels of the analog outputs. The voltage applied between these pins sets the full-scale output voltage. When this pin is HIGH, the analog output voltages are at or above V2. When this pin is LOW, the analog output voltages are at or below V1. Digital Power Supply. This pin is normally connected to the analog ground plane. Analog Power Supplies. Analog Supply Returns. A 0.1 F capacitor connected between this pin and AGND ensures optimum settling time. When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.
R/L E/O
Right/Left Select Even/Odd Select
XFR VID0-VID5 V1,V2 VREFHI, VREFLO INV DVCC DGND AVCCx AGNDx BYP STBY
Data Transfer Analog Outputs Reference Voltages Full-Scale References Invert Digital Power Supply Digital Supply Return Analog Power Supplies Analog Supply Returns Bypass Standby
Rev. 0 | Page 7 of 24
NC 24
AD8382
TYPICAL PERFORMANCE CHARACTERISTICS
1.00 0.75 0.50 0.25 OUTPUT (%) 7V OUTPUT (%) 0.00 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -20 0 20 40 60 80 100 120 140 160 180
1.50 1.25 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -20 0 20 40 60 80 100 120 140 160 180 2V
TIME (ns)
TIME (ns)
Figure 7. Output Settling Time (Rising Edge), CL = 200 pF, 5 V Step, INV = LOW
1.00 0.75 0.50 0.25 OUTPUT (%) 12V OUTPUT (%) 0.00 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -20 0 20 40 60 80 100 120 140 160 180
Figure 10. Output Settling Time (Falling Edge), CL = 200 pF, 5 V Step, INV = LOW
1.50 1.25 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -20 0 20 40 60 80 100 120 140 160 180 7V
TIME (ns)
TIME (ns)
Figure 8. Output Settling Time (Rising Edge), CL = 200 pF, 5 V Step, INV = HIGH
Figure 11. Output Settling Time (Falling Edge), CL = 200 pF, 5 V Step, INV = HIGH
0pF, 12V 47pF, 12V 100pF, 12V
OUTPUT (%) OUTPUT (%)
0pF, 7V 47pF, 7V
0.25%/DIV
150pF, 12V
0.25%/DIV
200pF, 12V 250pF, 12V 300pF, 12V
100pF, 7V 150pF, 7V 200pF, 7V 250pF, 7V 300pF, 7V
-15
0
15
30
45
60 TIME (ns)
75
90
105
120
135
-15
0
15
30
45
60 TIME (ns)
75
90
105
120
135
Figure 9. Output Settling Time (Rising Edge) vs. CL, 5 V Step, INV = HIGH
Figure 12. Output Settling Time (Falling Edge) vs. CL, 5 V Step, INV = HIGH
Rev. 0 | Page 8 of 24
AD8382
12 SWITCHING STEP RESPONSE (V) SWITCHING STEP RESPONSE (V) 2 20ns/DIV 2 20ns/DIV TIME (ns) 12
TIME (ns)
Figure 13. Invert Switching Step Response (Rising Edge), 10 V Step, CL = 200 pF
Figure 16. Invert Switching Step Response (Falling Edge), 10 V Step, CL = 200 pF
SWITCHING STEP RESPONSE (V)
7
SWITCHING STEP RESPONSE (V) 20ns/DIV
7
2
2
20ns/DIV
TIME (ns)
TIME (ns)
Figure 14. Data Switching Step Response (Rising Edge), 5 V Step, CL=200 pF, INV = LOW
Figure 17. Data Switching Step Response (Falling Edge), 5 V Step, CL = 200 pF, INV = LOW
SWITCHING STEP RESPONSE (V)
12
SWITCHING STEP RESPONSE (V) 20ns/DIV
12
7
7
20ns/DIV
TIME (ns)
TIME (ns)
Figure 15. Data Switching Step Response (Rising Edge), 5 V Step, CL = 200 pF, INV = HIGH
Figure 18. Data Switching Step Response (Falling Edge), 5 V Step, CL = 200 pF, INV = HIGH
Rev. 0 | Page 9 of 24
AD8382
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
DNL (LSB)
0
512
1024
1536
2048
2564
3072
3584
4096
DNL (LSB)
0
512
1024
1536
2048
2564
3072
3584
4096
INPUT CODE
INPUT CODE
Figure 19. Differential Nonlinearity (DNL) vs. Code, INV = LOW
Figure 22. Differential Nonlinearity (DNL) vs. Code, INV = HIGH
2.0 1.5 1.0 0.5 INL (LSB) 0 -0.5 -1.0 -1.5 -2.0 INL (LSB) 0 512 1024 1536 2048 2564 3072 3584 4096
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
0
512
1024
1536
2048
2564
3072
3584
4096
INPUT CODE
INPUT CODE
Figure 20. Integral Nonlinearity (INL) vs. Code, INV = LOW
Figure 23. Integral Nonlinearity (INL) vs. Code, INV = HIGH
3.500 2.625 1.750
VCME (mV)
5.00 3.75 2.50 1.25 VDE (mV) 0 512 1024 1536 2048 2564 3072 3584 4096 0
0.875 0
-0.875 -1.750 -2.625 -3.500
-1.25 -2.50 -3.75 -5.00
0
512
1024
1536
2048
2564
3072
3584
4096
INPUT CODE
INPUT CODE
Figure 21. Common-Mode Error Voltage (VCME) vs. Code
Figure 24. Differential Error Voltage (VDE) vs. Code
Rev. 0 | Page 10 of 24
AD8382
4 3 NORMALIZED VDE, VCME (mV)
4 3
NORMALIZED VDE, VCME (mV)
2 1 0 -1 -2 -3 -4 VCME
2 1 VDE 0 -1 -2 -3 -4 5.0 VCME
VDE
0
1.0
2.0
3.0 V2 - V1 (V)
4.0
5.0
6.0
6.0
7.0
8.0 V1 = V2 (V)
9.0
10.0
11.0
Figure 25. Normalized VDE, VCME vs. (V2 - V1) at Code 2048
Figure 28. Normalized VDE, VCME vs. V1 = V2 at Code 2048
10
4 3
NORMALIZED VDE, VCME (mV)
V1 = V2 = 5V, VFS = 3V 2 1 VCME 0 -1 -2 -3 VDE
NORMALIZED VDE (mV)
5
0
-5
-10
4
5
6
7
8
9
10
11
12
-4
5
6
7
8
9
10
11
12
13
14
V1 (V) @ V2 = 7V
V2 (V) @ V1 = 7V
VREFLO (V)
Figure 26. Normalized VDE vs. V1 and V2 at Code 2048
Figure 29. Normalized VDE, VCME vs. VREFLO at Code 2048
3.500 2.625 1.750
5.00 3.75 2.50 1.25
VCME (mV)
0.875 0
VDE (mV)
CODE 2048
0
CODE 2048
-0.875 -1.750 -2.625 -3.500
-1.25 -2.50 -3.75 -5.00
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 27. Common-Mode Error Voltage (VCME) vs. Temperature
Figure 30. Differential Error Voltage (VDE) vs. Temperature
Rev. 0 | Page 11 of 24
AD8382
7.05 7.04 7.03 7.02 7.01 V1 = V2 = 7V 20ns/DIV 7.05 7.04 7.03 7.02 7.01 V1 = V2 = 7V
VID (V)
7.00 6.09 VID0, 1, 2, 3 6.08 5V 6.07 6.06 6.05 TIME (ns)
VID (V)
(VID4 - VID5)
(VID4 - VID5) 7.00 6.09 6.08 6.07 6.06 6.05 TIME (ns) 20ns/DIV 3.3V DB (0:11)
Figure 31. All-Hostile Crosstalk at CL = 200 pF
Figure 34. Data Switching Transient (Feedthrough) at CL = 200 pF
800
900 800 700
700
SLEW RATE (V/s)
SLEW RATE (V/s)
600
600 500 10% TO 90% 400 20% TO 80% 300 200
500 10% TO 90% 400 20% TO 80% 300
200
0
50
100
150
200
250
300
0
50
100
150
200
250
300
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 32. Slew Rate vs. CL (Falling Edge)
Figure 35. Slew Rate vs. CL (Rising Edge)
0 -10 -20 -30
PSR (dB)
-40 INV = LOW -50 INV = HIGH -60 -70 -80 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. AVCC Power Supply Rejection vs. Frequency
Rev. 0 | Page 12 of 24
AD8382
FUNCTIONAL DESCRIPTION
The AD8382 is a system building block designed to directly drive the columns of LCD microdisplays of the type popularized for use in projection systems. It comprises six channels of precision, 12-bit digital-to-analog converters loaded from a single, high speed, 12-bit wide input. Precision current feedback amplifiers, providing well-damped pulse response and fast voltage settling into large capacitive loads, buffer the six outputs. Laser trimming at the wafer level ensures low absolute output errors and tight channel-to-channel matching. Tight part-to-part matching in high resolution systems is guaranteed by the use of external voltage references.
V1, V2 INPUTS--VOLTAGE REFERENCE INPUTS
Two external analog voltage references set the levels of the outputs. V1 sets the output voltage at Code 4095 while the INV input is LOW, and V2 sets the output voltage at Code 4095 while the INV input is held HIGH.
VREFHI, VREFLO INPUTS--FULL-SCALE REFERENCE INPUTS
Twice the difference between these analog input voltages sets the full-scale output voltage VFS.
VFS = 2 x (VREFHI - VREFLO)
START SEQUENCE CONTROL--INPUT DATA LOADING
A valid STSQ control input initiates a new 6-clock loading cycle, during which six input data-words are loaded sequentially into six internal channels. A new loading sequence begins on the current active CLK edge only when STSQ was held HIGH at the preceding active CLK edge. Active CLK edge is defined by the E/O Control.
INV CONTROL--ANALOG OUTPUT INVERSION
The analog voltage equivalent of the input code is subtracted from (V2 + VFS) while INV is held HIGH and added to (V1 - VFS) while INV is held LOW.
Transfer Function
The AD8382 has two regions of operation, where the video output voltages are either above reference voltage V2 or below reference voltage V1. The transfer function defines the video output voltage as the function of the digital input code as follows:
VIDx(n) = V2 + VFS x (1 - n/4095), for INV = HIGH VIDx(n) = V1 - VFS x (1 - n/4095), for INV = LOW
EVEN/ODD CONTROL--INPUT DATA LOADING
To facilitate 12-channel, single data bus systems, the active CLK edge, at which input data is loaded, is selected with the E/O control input. Input data is loaded on the rising CLK edges while the E/O input is held HIGH; input data is loaded on the falling CLK edges while the E/O input is held LOW.
RIGHT/LEFT CONTROL--INPUT DATA LOADING
To facilitate image mirroring, the direction of the loading sequence is set by the R/L control. A new loading sequence begins at channel 0 and proceeds to Channel 5 when the R/L control is held LOW. It begins at Channel 5 and proceeds to channel 0 when the R/L control is held HIGH.
where n = input code
VFS = 2 x (VREFHI - VREFLO)
A number of internal limits define the usable range of the video output voltages, VIDx, as shown in Figure 36
AVCC 1.3V
XFR CONTROL--DATA TRANSFER TO OUTPUTS
Data transfer to the outputs is initiated by the XFR control. While XFR is held HIGH during a rising CLK edge, data is simultaneously transferred to all outputs on the immediately following falling CLK edge.
V2 + VFS
INV = HIGH
INTERNAL LIMITS AND USABLE VOLTAGE RANGES
0 VFS 5.5V
VIDx (V)
9V AVCC 18V
V2 5V V2 (AVCC - 4) V1 0 VFS 5.5V INV = LOW 5V V1 (AVCC - 4) 1.3V
STBY CONTROL--STANDBY MODE
A HIGH applied to the STBY input debiases the internal circuitry, dropping the quiescent power dissipation to a few milliwatts. Upon returning STBY to LOW, normal operation is restored. Since both analog and digital circuitry is debiased, all stored data will be lost in standby mode.
V1 - VFS
AGND 0 INPUT CODE
4095
Figure 36. Transfer Function and Usable Voltage Ranges
Rev. 0 | Page 13 of 24
AD8382
Accuracy
To best correlate transfer function errors to image artifacts, the overall accuracy of the AD8382 is defined by three parameters: VDE, VCME, and V.
VDE, the differential error voltage, measures the difference between the rms value of the output and the rms value of the ideal. The defining expression is:
AVCC
(V2 + VFS)
VIDx (V)
V2 VOUTN(n) V1
VDE(n) =
[VOUTN (n) - V 2] - [VOUTP(n) - V 1] n - 1 - x VFS 2 4095
(V1 - VFS)
VOUTP(n)
VCME, the common-mode error voltage, measures one-half the dc bias of the output. The defining expression is: VCME(n) = 1 VOUTN (n) +VOUTP(n) (V 2 +V 1) - 2 2 2
AGND
0
n INPUT CODE
4095
Figure 37. AD8382 Transfer Function
V measures the maximum deviation between the output voltages. The defining expression is: V (n) = max{VN(n), VP(n)} where VN(n) = max{VOUTN(n)(0-5)} - min{VOUTN(n)(0-5)} and VP(n) = max{VOUTP(n)(0-5) } - min{VOUTP(n)(0-5)}
Rev. 0 | Page 14 of 24
AD8382
APPLICATIONS
OPERATING MODES--6-CHANNEL SYSTEMS
Depending on the speed of the LCD microdisplay, 6-channel systems are compatible with up to XGA resolutions and require one AD8382 per color. The input/output timing diagram of the AD8382 in such systems is shown in Figure 38.
DB(0:11) -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK STSQ XFRF
PIXEL CLK DB(0:11) -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CLK STSQ STSQ
INPUTS
INPUTS
XFR R/L E/O EVEN
INTERNAL LATCHES
CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 VID0 VID1 -1 -6 -5 -4 -3 -2 -1
0 1 2 3 4 5 0 1 2 3 4 5
6 7 8
12
E/O ODD
AD8382 EVEN INTERNAL LATCHES
9 10 11 6 7 8 9 10 11
CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 VID0 VID1 VID2 VID3 VID4 VID5 -2
0 2 4 6 8 10 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10
12 14 16 18 20 22 12 14 16 18 20 22
OUTPUTS
VID2 VID3 VID4 VID5
Figure 38. Timing Diagram in a Typical 6-Channel System, E/O=HIGH, R/L=LOW
AD8382 ODD INTERNAL LATCHES
OPERATING MODES--12-CHANNEL SYSTEMS
12-channel systems are usually those requiring video line doubling or compatibility with SXGA and higher resolutions. Depending on the input data rates, two types of 12-channel systems are in common use.
OUTPUTS
CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 VID0 VID1 VID2 VID3 VID4 VID5 -3 -1 -11 -9 -7 -5 -3 -1
1 3 5 7 9 11 1 3 5 7 9 11
13 15 17 19 21 23 13 15 17 19 21 23
12-Channel, Even/Odd Systems
Single data bus systems are characterized by an image processor with a single data bus output. They require two AD8382s per color. One AD8382 is set to operate in EVEN mode, while the other is set to operate in ODD mode. Both AD8382s share the same data bus and CLK. The timing diagram of such a system is shown in Figure 39.
OUTPUTS
Figure 39. 12-Channel Even/Odd System Timing Diagram
OPERATING MODES--BEYOND 12 CHANNELS
12-Channel Parallel Systems
Dual data bus systems are characterized by an image processor with two data bus outputs. They require two AD8382s per color. Both AD8382s in dual data bus systems can be set independently. The timing diagram of each AD8382 in such systems is identical to that of a 6-channel system. Any number of AD8382s may be cascaded in even/odd pairs or in parallel to facilitate very high resolution systems.
Rev. 0 | Page 15 of 24
AD8382
IMAGE PROCESSOR STSQ2 STSQ1 Pixel CLK /2 DB1(0:11) CLK XFR R/L STSQ1 INV1 E/O1 STSQ2 INV2 E/O2 DB(0:11) CLK XFR R/L STSQ INV E/O VREFHI VREFLO V2 V1 VID0 VID1 VID2 VID3 VID4 VID5 Ch 0 Ch 2 Ch 4 Ch 6 Ch 8 Ch 10
AD8382
CLK CLK H. REVERSE CLK CLK
/6 COUNTER
/6 COUNTER HSTART
12 - CHANNEL LCD
AD8382
DB(0:11) VID0 HSYNC VSYNC INV1 INV2 CLK XFR R/L STSQ INV E/O VREFHI VREFLO V2 V1 VID1 VID2 VID3 VID4 VID5 CH 1 CH 3 CH 5 CH 7 CH 9 CH 11
REFERENCES VREFHI VREFLO V2 V1
Figure 40. Single Data Bus 12-Channel Even/Odd System Block Diagram
IMAGE PROCESSOR D(0:9) Odd D(0:9) Even Pixel CLK /2 H. REVERSE CLK /6 COUNTER HSTART "1" DB1(0:11) CLK XFR R/L STSQ INV1 E/O INV2 DB(0:11) CLK XFR R/L STSQ INV E/O VREFHI VREFLO V2 V1
AD8382
VID0 VID1 VID2 VID3 VID4 VID5 Ch 0 Ch 2 Ch 4 Ch 6 Ch 8 Ch 10
12 - CHANNEL LCD
AD8382
D(0:9) Even D(0:9) Odd HSYNC VSYNC INV1 INV2 DB2(0:11) DB(0:11) VID0 CLK XFR R/L STSQ INV E/O VREFHI VREFLO V2 V1 VID1 VID2 VID3 VID4 VID5 CH 1 CH 3 CH 5 CH 7 CH 9 CH 11
REFERENCES VREFHI VREFLO V2 V1
Figure 41. Dual Data Bus 12-Channel Even/Odd System Block Diagram
Rev. 0 | Page 16 of 24
AD8382
VBIAS Generation--V1, V2 Input Pin Functionality
In order to avoid image flicker, a symmetrical ac voltage is required and a bias voltage of approximately 1 V minimum must be maintained across the pixels of HTPS LCDs. The AD8382 provides two methods of maintaining this bias voltage.
APPLICATIONS CIRCUIT
The circuit in Figure 41 ensures VBIAS symmetry to within 1 mV with a minimum component count. Bypass capacitors are omitted for clarity.
AVCC = 15.5V
VZ = 5.1V
INTERNAL BIAS VOLTAGE GENERATION
Standard systems that internally generate the bias voltage reserve the uppermost code range for the bias voltage and use the remaining code range to encode the video for gamma correction. A high degree of ac symmetry is guaranteed by the AD8382 in these systems. The V1 and V2 inputs in these systems are tied together and are normally connected to VCOM, as shown in Figure 42.
1 VCOM = 7V R2 = 1k 3 -IN V+ 5
AD8382
V2 = 8V V2
2 VCOM AD8132 8 +IN V- 6 4 V1 = 6V V1
R1 = 6k DVCC = 3.3V
Figure 43. External VBIAS Generator with the AD8132
VFS = 5V
AD8382
VCOM V2 V1 VCOM VBIAS = 1V VBIAS = 1V 3280 4095
VFS = 4V V2
VFS = 5V
RESERVED CODE RANGE
VCOM V1 VFS = 4V
VBIAS = 1V VBIAS = 1V 4095
Figure 42. V1, V2 Connection and Transfer Function in a Typical Standard System
EXTERNAL BIAS VOLTAGE GENERATION
In systems that require improved brightness resolution and higher accuracy, the V1 and V2 inputs, connected to external voltage references, provide necessary bias voltage, VBIAS, while allowing the full code range to be used for gamma correction.
Figure 44. The AD8382 Transfer Function in a Typical High Accuracy System
8.75 7.50 6.25 5.00
(V2 + V1)/2 - VCOM (mV)
3.75 2.50 1.25 0.00 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 5.7 6.2 6.7 7.2
To ensure a symmetrical ac voltage at the AD8382's outputs, VBIAS must remain constant for both states of INV. Thus, V1 and V2 are defined as: V1 = VCOM - VBIAS V2 = VCOM + VBIAS
TA = 85C
TA = 25C
7.7
8.2
8.7
9.2
9.7
10.2
10.7
V+ - V- (V)
Figure 45. Typical Asymmetry at the Outputs of the AD8132 vs. Power Supply for the Application Circuit
The AD8132 typically produces a symmetrical output at 85C when its supply, (V+) - (V-), is 7.2 V (Figure 45).
Rev. 0 | Page 17 of 24
AD8382
Power Supply Sequencing
As indicated in the Absolute Maximum Ratings, voltage at any input pin cannot exceed its supply voltage by more than 0.5 V. To ensure compliance with these ratings, the following powerup and power-down sequencing is recommended. During power-up, initial application of nonzero voltages to any input pin must be delayed until supply voltage ramps up to at least the highest maximum operational input voltage. During power-down, the voltage at any input pin must reach zero during a period not exceeding the power supply's hold-up time. Failure to comply with the Absolute Maximum Ratings may result in functional failure or damage to the internal ESD diodes. Damaged ESD diodes may cause temporary parametric failures, which may result in image artifacts. Damaged ESD diodes cannot provide full ESD protection, reducing reliability.
Power ON Power OFF
The AD8382 package is designed to provide superior thermal characteristics, partly through the exposed die paddle on the bottom surface of the package. In order to take full advantage of this feature, the exposed paddle must be in direct thermal contact with the PCB, which then serves as a heat sink.
Table 5. AD8382 Power Dissipation
CLOAD (pF) 200 250 300 PQUIESCENT (W) 0.74 0.74 0.74 VSWING = 5 V PDYNAMIC PTOTAL (W) (W) 0.93 1.67 1.16 1.90 1.39 2.13 VSWING = 4 V PDYNAMIC PTOTAL (W) (W) 0.74 1.48 0.93 1.67 1.11 1.85
A thermally effective PCB must incorporate a thermal pad and a thermal via structure. The thermal pad provides a solderable contact surface on the top surface of the PCB. The thermal via structure provides a thermal path to the inner and bottom layers of the PCB to remove heat.
1. Apply power to supplies. 2. Apply power to other I/Os.
1. Remove power from I/Os. 2. Remove power from supplies.
THERMAL PAD DESIGN
Thermal performance of the AD8382 varies logarithmically with the contact area between the exposed thermal paddle and the thermal pad on the top layer of the PCB. In order to minimize thermal performance degradation of production PCBs, the contact area between the thermal pad and the PCB should be maximized. Therefore, the size of the thermal pad should match the exposed paddle size of 5.25 mm x 5.25 mm. In addition, a second thermal pad of the same size should be placed on the bottom side of the PCB. At least one thermal pad should be in direct thermal (and electrical) contact with the AVCC plane.
PCB Design for Optimized Thermal Performance
The total maximum power dissipation of the AD8382 is partly load dependent. In a 6-channel, 65 MHz, 60 Hz XGA system, the total maximum power dissipation is 1.14 W at an LCD input capacitance of 200 pF. At a clock rate of 120 Ms/s, the total maximum power dissipation can exceed 2 W, as shown below for a black-to-white video output voltage swing of 4 V and 5 V. Although the maximum safe operating junction temperature is higher, the AD8382 is 100% tested at a junction temperature of 125C. Consequently, the maximum guaranteed operating junction temperature is 125C. To limit the maximum junction temperature at or below the guaranteed maximum, the package, in conjunction with the PCB, must effectively conduct heat away from the junction.
THERMAL VIA STRUCTURE DESIGN
Effective heat transfer from the top to the inner and bottom layers of the PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmically with the number of vias. JA reaches its specified value at approximately 16 vias, provided the AD8382 is on a standard JEDEC PCB. JA approaches its optimum value as the slope of such a curve approaches zero, at above 36 vias. Near optimum thermal performance of production PCBs is attained when the number of thermal vias is at least 36.
Rev. 0 | Page 18 of 24
AD8382
AD8382 PCB DESIGN RECOMMENDATIONS
7 mm
SOLDER MASKING
To minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), via diameter should be small. Solder masking of the via holes on the top layer of the PCB plugs the via holes, inhibiting solder flow into the holes. To optimize the thermal pad coverage, the solder mask diameter should be no more than 0.1 mm larger than the via diameter.
Land pattern Dimensions Pad Size: 0.5 mm x 0.25 mm
7 mm
Pad Pitch: 0.5 mm Thermal Pad Size: 5.25 mm x 5.25 mm Thermal via structure: 0.25 mm diameter. Vias on 0.5mm grid.
Solder Mask--Top Layer
Pads: Set by customer's PCB Design Rules
LAND PATTERN - TOP LAYER
Figure 46. Land Pattern--Top Layer
Thermal Vias: 0.25 mm dia. circular mask, centered on the vias.
THERMAL PAD AND VIA CONNECTIONS
Thermal Pads are connected to AVCC. For PCBs with the AVCC plane located on one of the outer layers, direct connection of at least one thermal pad to the AVCC plane is recommended. For PCBs with the AVCC plane located on one of the internal layers, direct connection of all thermal vias to the AVCC plane is recommended.
Solder Mask--Bottom Layer
Set by customer's PCB Design Rules.
SOLDER MASK - TOP LAYER
Figure 48. Solder Mask--Top Layer
LAND PATTERN - BOTTOM LAYER
Figure 47. Land Pattern--Bottom Layer
The use of thermal spokes is not recommended when connecting the thermal pads or via structure to the AVCC plane.
Rev. 0 | Page 19 of 24
AD8382
Layout Considerations
The AD8382 is a mixed-signal, high speed, high accuracy device. In order to fully realize its specifications, it is essential to use a properly designed printed circuit board.
POWER SUPPLY BYPASSING
All power supply and reference pins of the AD8382 must be properly bypassed to the analog ground plane for optimum performance. All analog supply pins may be connected directly to an analog supply plane located as close to the part as possible. A 0.1 F chip capacitor should be placed as close to each analog supply pin as possible and connected directly between each analog supply pin and the analog ground plane. A minimum 47 F tantalum capacitor should be placed near the analog supply plane and connected directly between the supply and analog ground planes. A minimum 10 F tantalum capacitor should be placed near the digital supply pin and connected directly to the analog ground plane. A 0.1 F chip capacitor should be connected between the digital supply pin and the analog ground.
LAYOUT AND GROUNDING
The analog outputs and the digital inputs of the AD8382 are on opposite sides of the package. Keep these sections separated to minimize crosstalk and coupling of digital inputs into the analog outputs. All signal trace lengths should be made as short and direct as possible to prevent signal degradation due to parasitic effects. Note that digital signals should not cross and should not be routed near analog signals. It is imperative to provide a solid analog ground plane under and around the AD8382. All ground pins of the part should be connected directly to this ground plane with no extra signal path length. This includes DGND, AGNDBIAS, AGND5, AGND3,4, AGND1,2, AGND0, and AGNDDAC. The return traces for any of the signals should be routed close to the ground pin for that section to prevent stray signals from coupling into other ground pins.
VREFHI, VREFLO, V2, V1 REFERENCE DISTRIBUTION
To ensure well-matched video outputs, all AD8382s must operate from equal reference voltages. Each reference voltage should be distributed to each AD8382 directly from the source of the reference voltage with approximately equal trace lengths. A 0.1 F chip capacitor should be placed as close to each reference input pin as possible and directly connected between the reference input pin and the analog ground plane.
Rev. 0 | Page 20 of 24
AD8382
OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTO M VIEW
5.25 5.10 SQ 4.95
0.50 0.40 0.30 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08
25 24
12 13
1.00 0.90 0.80 0.20 REF
5.50 REF
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 49. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)--Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8382 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ordering Guide
Table 6.
Model AD8382ACP Temperature Range 0C to 85C Package Description 48-Lead LFCSP Package Option CP-48
Rev. 0 | Page 21 of 24
AD8382
Rev. 0 | Page 22 of 24
AD8382
Rev. 0 | Page 23 of 24
AD8382
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C03371-0-2/03(0)
Rev. 0 | Page 24 of 24

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